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Proceedings Paper

Optimal sampling strategies for sub-100-nm overlay
Author(s): Bharath Rangarajan; Michael K. Templeton; Luigi Capodieci; Ramkumar Subramanian; Alec B. Scranton
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Paper Abstract

Overlay control is a critical requirement of the lithographic process, and the challenge will be even greater with 0.18- micron technology, where the overlay budget is expected to shrink to 70 nm. Control of overlay is often achieved by modifying the stepping parameters to remove any correctable overlay errors. The estimated value of these parameters depends on the overlay error between the two layers, the model used, and the overlay-sampling plan. Overlay sampling strategies face the following dilemma: plans that sample overlay at the edge of the wafer or field will show atypically large overlay errors, but these plans can result in more accurate estimates of the correctable terms. Therefore when measuring overlay at these extreme points the lithographer needs to recognize that this type of sampling will typically indicate that overlay is substantially worse than it is in the average field. In this paper, a number of different sampling plans that measure 25 points on a wafer were tested. The results obtained from the various plans have been compared to the results obtained from measuring the entire wafer. The data show that the sampling pattern can have a significant effect on the values of the various correctable parameters, and that an inappropriate sampling plan can consume a significant portion of the overlay budget. We have identified several effective sampling patterns, and the improved performance of these plans is attributed to the fact that these patterns achieve greater coverage of the wafer and measure a large number of wafer (or grid) points than the other sampling plans.

Paper Details

Date Published: 8 June 1998
PDF: 12 pages
Proc. SPIE 3332, Metrology, Inspection, and Process Control for Microlithography XII, (8 June 1998); doi: 10.1117/12.308743
Show Author Affiliations
Bharath Rangarajan, Advanced Micro Devices, Inc. (United States)
Michael K. Templeton, Advanced Micro Devices, Inc. (United States)
Luigi Capodieci, Advanced Micro Devices, Inc. (United States)
Ramkumar Subramanian, Advanced Micro Devices, Inc. (United States)
Alec B. Scranton, Michigan State Univ. (United States)

Published in SPIE Proceedings Vol. 3332:
Metrology, Inspection, and Process Control for Microlithography XII
Bhanwar Singh, Editor(s)

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