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Proceedings Paper

Mapping of video decoder software on a VLIW DSP multiprocessor
Author(s): Achim Freimann; Thomas Brune; Peter Pirsch
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Paper Abstract

When implementing today's video compression standards on programmable processors, it is essential to optimize the algorithms with respect to the underlying hardware. As an example, the core decoder functions of the H.263 hybrid coding scheme were implemented on a SIMD controlled processor with four parallel VLIW data paths, the HiPAR-DSP. The decoder tasks were implemented employing local memory, parallelization on several levels, and data statistics. Special effort was paid on the computation intensive tasks IDCT, and motion compensated frame reconstruction. To speed up the IDCT computation, a data dependent approach was chosen, which distinguishes different block types. The determination of IDCT block type could be parallelized together with other tasks, thus no additional overhead is required. Frame reconstruction mainly benefits from data parallel operations and transparent DMA transfers to and from external memory.

Paper Details

Date Published: 26 March 1998
PDF: 12 pages
Proc. SPIE 3311, Multimedia Hardware Architectures 1998, (26 March 1998); doi: 10.1117/12.304662
Show Author Affiliations
Achim Freimann, Univ. Hannover (Germany)
Thomas Brune, Deutsche Thomson-Brandt GmbH (Germany)
Peter Pirsch, Univ. Hannover (Germany)


Published in SPIE Proceedings Vol. 3311:
Multimedia Hardware Architectures 1998
Sethuraman Panchanathan; Frans Sijstermans; Subramania I. Sudharsanan, Editor(s)

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