Share Email Print
cover

Proceedings Paper

Parallelism analysis of the memory system in single-chip VLIW video signal processors
Author(s): Zhao Wu; Wayne H. Wolf
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This paper presents a design study of the memory system for a very long instruction word (VLIW) video signal processor (VSP). The gap between memory and modern processors is continuously becoming wider and wider, and thus memory systems have been a subject of active research for a long time.However, memory issues in VLIW machines have not yet been addressed. Real-time video signal processing requires a fast memory with high-bandwidth and high-connectivity. Efficient memory system design is particularly important for VSPs that combine significant amounts of memory on-chip with the processor, which we expect to become common in the next generation of VSPs. In this paper we use trace-driven methodology to analyze the parallelism, especially that of memory operations, in video applications. With a scheduling range of up to ne billion operations, we analyzed large traces of several real applications including H.263, MPEG2 and MPEG4. We found that even with a conservative configuration the average speedup is more than 8.

Paper Details

Date Published: 26 March 1998
PDF: 9 pages
Proc. SPIE 3311, Multimedia Hardware Architectures 1998, (26 March 1998); doi: 10.1117/12.304661
Show Author Affiliations
Zhao Wu, Princeton Univ. (United States)
Wayne H. Wolf, Princeton Univ. (United States)


Published in SPIE Proceedings Vol. 3311:
Multimedia Hardware Architectures 1998
Sethuraman Panchanathan; Frans Sijstermans; Subramania I. Sudharsanan, Editor(s)

© SPIE. Terms of Use
Back to Top