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Proceedings Paper

High-speed image processing algorithms using MMX hardware
Author(s): John W. V. Miller; James Wood
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Paper Abstract

Low-cost PC-based machine vision systems have become more common due to faster processing capabilities and the availability of compatible high-speed image acquisition and processing hardware. One development, which is likely to have a very favorable impact on this trend, is enhanced multimedia capabilities present in new processor chips such as Intel MMX and Cyrix M2 processors. Special instructions are provided with this type of hardware which, combined with a SIMD parallel processing architecture, provides a substantial speed improvement over more traditional processors. Eight simultaneous byte or four double-byte operations are possible. The new instructions are similar to those provided by DSP chips such as multiply and accumulate and are quite useful for linear processing operations like convolution. However, only four pixels may be processed simultaneously because of the limited dynamic range of byte data. Given the inherent limitations with respect to looping in SIMD hardware, nonlinear operations such as erosion and dilation would seem to be difficult to implement. However, special instructions are available for required operations. Benchmarks for a number of image-processing operations are provided in the paper to illustrate the advantages of the new multimedia extensions for vision applications.

Paper Details

Date Published: 18 September 1997
PDF: 8 pages
Proc. SPIE 3205, Machine Vision Applications, Architectures, and Systems Integration VI, (18 September 1997); doi: 10.1117/12.285568
Show Author Affiliations
John W. V. Miller, Univ. of Michigan/Dearborn (United States)
James Wood, Univ. of Michigan/Dearborn (United States)


Published in SPIE Proceedings Vol. 3205:
Machine Vision Applications, Architectures, and Systems Integration VI
Susan Snell Solomon; Bruce G. Batchelor; John W. V. Miller, Editor(s)

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