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Proceedings Paper

Die-counting algorithm for yield modeling and die-per-wafer optimization
Author(s): Gregg D. Croft; Robert L. Lomenick; Douglas L. Youngblood; Jeffrey M. Johnston
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Paper Abstract

This paper presents a computer algorithm for accurately counting the total number of possible yielding die sites on a wafer. This algorithm takes into account such variables as the X and Y die dimensions, the size and orientation of the wafer flat(s), the size of the non-yielding periphery zone, and the position of the die array relative to the center of the wafer. This algorithm can be used in conjunction with a variety of different yield models to increase each model's ability to predict accurate die per wafer yields. In addition to applications in yield modeling, this die counting algorithm may also be used as a tool for increasing yields or decreasing circuit layout cycle time. Several examples of these alternate applications are presented.

Paper Details

Date Published: 11 September 1997
PDF: 11 pages
Proc. SPIE 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III, (11 September 1997); doi: 10.1117/12.284701
Show Author Affiliations
Gregg D. Croft, Harris Semiconductor (United States)
Robert L. Lomenick, Harris Semiconductor (United States)
Douglas L. Youngblood, Harris Semiconductor (United States)
Jeffrey M. Johnston, Harris Semiconductor (United States)


Published in SPIE Proceedings Vol. 3216:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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