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Proceedings Paper

STADIUM SOI reliability simulator for the analysis of hot-electron and ESD-induced degradation in nonisothermal devices
Author(s): David Lee; Thomas J. Sanders
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Paper Abstract

This paper addresses the integrated circuit industry needs for non-isothermal simulation in device reliability analysis, initial input factor sensitivity analysis and their software implementation. The key reliability issues are the hot-electron induced oxide damages and electro-static discharge (ESD) damages. The main purpose of this work is to provide a design aid tool to improve device reliability and performance. The reliability simulator developed in this work not only predicts designed device reliability, but also provides some information about the effect of manufacturing variations on reliability. This is accomplished by combining the statistical methodology with existing technology computer aided design (TCAD) tools. The design of experiment (DoE) technique can be successfully employed to analyze the effect of manufacturing variations on the SOT device reliability. As an example, the reliability analysis and the statistical analysis have performed on SOT MOS devices (partially depleted and fully depleted SOT) and submicron bulk-Si MOSFET's to verify the applied modeling method.

Paper Details

Date Published: 11 September 1997
PDF: 10 pages
Proc. SPIE 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III, (11 September 1997); doi: 10.1117/12.284692
Show Author Affiliations
David Lee, Florida Institute of Technology (United States)
Thomas J. Sanders, Florida Institute of Technology (United States)


Published in SPIE Proceedings Vol. 3216:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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