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Proceedings Paper

Evaluation of pad life in chemical mechanical polishing process using statistical metrology
Author(s): N. Moorthy Muthukrishnan; Sharad Prasad; Brian Stine; William Loh; Ron Nagahara; James E. Chung; Duane S. Boning
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Paper Abstract

Statistical meirology was used to characterize the pad life in chemical mechanical polishing process. A special chip containing capacitor structures with dimensions laid out as per a fractional factorial design of experiment was used as a lest vehicle in this study. The wafer lot was separated into four splits and each split was polished at a different time depending on the wafer count since the last pad change in the chemical mechanical polishing system. Capacitance measurements were done on the test capacitors and the IMD thickness was determined from the 2D simulation of the capacitor. The wafer-level and die-level variations were determined using an application software program known as Variation Decomposition Analysis Program . The useful pad life can be determined by selecting the wafer count below which inter- and intra-die variations are allowable.

Paper Details

Date Published: 11 September 1997
PDF: 10 pages
Proc. SPIE 3216, Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III, (11 September 1997); doi: 10.1117/12.284688
Show Author Affiliations
N. Moorthy Muthukrishnan, LSI Logic Corp. (United States)
Sharad Prasad, LSI Logic Corp. (United States)
Brian Stine, Massachusetts Institute of Technology (United States)
William Loh, LSI Logic Corp. (United States)
Ron Nagahara, LSI Logic Corp. (United States)
James E. Chung, Massachusetts Institute of Technology (United States)
Duane S. Boning, Massachusetts Institute of Technology (United States)


Published in SPIE Proceedings Vol. 3216:
Microelectronic Manufacturing Yield, Reliability, and Failure Analysis III
Ali Keshavarzi; Sharad Prasad; Hans-Dieter Hartmann, Editor(s)

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