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Proceedings Paper

Monitoring process-induced oxide breakdown and its correlation to interface traps
Author(s): Artur P. Balasinski; R. Hodges; J. Walters; Charles R. Spinner
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Paper Abstract

In-line testing methods of thin gate oxide integrity are compared based on oxide breakdown characteristics. The results were obtained on test structures with plasma induced oxide degradation due to the different plasma based deposition and etch processes used in the five metal CMOS fabrication. Voltage ramp technique has been identified as the most sensitive and universal technique to investigate breakdown characteristics. In order to find out about the possible correlation between the degradation of oxide bulk and the Si/SiO2 interface, trap density in MOSFETs was also monitored using transconductance and charge pumping measurements. It was found that while interface degradation was indeed more severe in the structures showing lower breakdown voltages, no quantitative relationship with breakdown voltage could be established. Process-induced defect distribution across the wafers will also be discussed.

Paper Details

Date Published: 2 September 1997
PDF: 8 pages
Proc. SPIE 3215, In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing, (2 September 1997); doi: 10.1117/12.284673
Show Author Affiliations
Artur P. Balasinski, SGS Thomson Microelectronics (United States)
R. Hodges, SGS Thomson Microelectronics (United States)
J. Walters, SGS Thomson Microelectronics (United States)
Charles R. Spinner, SGS Thomson Microelectronics (United States)

Published in SPIE Proceedings Vol. 3215:
In-Line Characterization Techniques for Performance and Yield Enhancement in Microelectronic Manufacturing
Damon K. DeBusk; Sergio A. Ajuria, Editor(s)

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