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Proceedings Paper

Tungsten CMP process characterization for sub-0.35-um micron technology
Author(s): Christopher Chia; Jia Zhen Zheng; Wei Jiang; Yan Tse Tak
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Paper Abstract

The chemical mechanical polishing (CMP) of tungsten has been recognized as an enabling technology for sub-half-micron multi-level interconnect. There are many technical challenges to be resolved when incorporating tungsten CMP into the manufacturing line. In this paper, key issues related to the tungsten CMP process--oxide erosion, plug recess, oxide thinning, surface roughness, microscratches, contamination, photolithographic alignment, metal line bridging, via resistance and device yield--were studied for three different types of slurries. The variables studied include pattern density, glue layer thickness, overpolish time and underlying oxide type. Atomic force microscopy, scanning electron microscope and long-scan surface profiler were used. Oxide thinning and erosion were found to depend strongly on slurry type and all the variables studied. With optimized polishing parameters and integration scheme, the tungsten CMP process has enough processing window for manufacturing.

Paper Details

Date Published: 5 September 1997
PDF: 7 pages
Proc. SPIE 3214, Multilevel Interconnect Technology, (5 September 1997); doi: 10.1117/12.284666
Show Author Affiliations
Christopher Chia, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Jia Zhen Zheng, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Wei Jiang, Chartered Semiconductor Manufacturing, Ltd. (Singapore)
Yan Tse Tak, Chartered Semiconductor Manufacturing, Ltd. (Singapore)


Published in SPIE Proceedings Vol. 3214:
Multilevel Interconnect Technology
Divyesh N. Patel; Mart Graef, Editor(s)

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