Share Email Print

Proceedings Paper

Electroless Cu and barrier layers for subhalf-micron multilevel interconnects
Author(s): Sergey D. Lopatin; Yosef Y. Shacham-Diamand; Valery M. Dubin; P. K. Vasudev
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Characteristics of electroless Cu, Co and Ni alloys for a multilevel metallization as well as for local interconnects and silicide formations for sub-0.5 micrometers ULSIs are presented. An integration of the electroless Cu and CoWP multilayers in an ULSI damascene process for the quarter-micron Cu interconnects of aspect ratio 4:1 is discussed. The following techniques are involved in this process: conformal electroless deposition of CoWP barrier on the thin sputtered Co seed layer, electroless Cu deposition directly onto CoWP barrier to fill a deep trench or a via, removal of the excess barrier and Cu on the oxide by chemical mechanical polishing, Pd activation of the Cu surface and selective electroless CoWP deposition onto Pd- activated in-laid Cu lines to prevent Cu oxidation and corrosion. The study of the selective electroless NiP deposition on Si for silicide formations for sub-0.25micrometers ULSI technology is also presented.

Paper Details

Date Published: 5 September 1997
PDF: 12 pages
Proc. SPIE 3214, Multilevel Interconnect Technology, (5 September 1997); doi: 10.1117/12.284661
Show Author Affiliations
Sergey D. Lopatin, Cornell Univ. (United States)
Yosef Y. Shacham-Diamand, Cornell Univ. (Israel)
Valery M. Dubin, Advanced Micro Devices, Inc. (United States)
P. K. Vasudev, SEMATECH (United States)

Published in SPIE Proceedings Vol. 3214:
Multilevel Interconnect Technology
Divyesh N. Patel; Mart Graef, Editor(s)

© SPIE. Terms of Use
Back to Top