Share Email Print
cover

Proceedings Paper

Removal of surface oxide from electrical test (E-test) pads using an argon sputter etch procedure to recover TAB wafers
Author(s): Tina A. Petersen-Buchheit; William R. Johannes; Divyesh N. Patel; Jeffrey F. Coleman
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

In Intel's manufacturing flow, discrete devices in the scribeline of wafers are tested (E-Test structures) to determine if they meet specifications for reliability and functionality. The wafers are then sorted to determine die functionality. Probing equipment is used to measure E-test structures by way of aluminum pads (E-Test pads) which make contact with devices in the scribeline. Tape automated bonding packaging requires additional processing (compared to Wire Bonded devices) to plate gold bumps on to the die bond pads. The gold bumps are not plated on the E-Test pads but they receive additional processing which may create an insulating surface layer, such as aluminum oxide, preventing the acquisition of reliability information from the wafer tested. If reliability data is not available, wafers are discarded even though the die present on the wafer may be functional. An argon sputter etch procedure is suggested to remove the problematic insulating oxide and recover wafers. The major concerns associated with using a sputter etch recovery procedure include: redistribution of gold across the surface of the wafer; gate charging due to the sputter process; polyimide (PI) surface roughness and thickness issues; encapsulation adhesion issues; and elevated burn-in fallout. This paper will discuss the procedure used to remove surface oxide and experiments to determine if recovery was successful. Process characterization which encompassed etch time and RF power were used to optimize the recovery procedure for reliability purposes. The experimental parameters evaluated include: E-Test parametric data to compare recovered wafers to baseline wafers; threshold voltage data; pad to pad surface leakage due to gold redistribution; SEM cross sections and profilometry to ensure PI integrity; and C-mode Scanning Acoustic Microscopy to address encapsulation adhesion concerns.

Paper Details

Date Published: 5 September 1997
PDF: 9 pages
Proc. SPIE 3214, Multilevel Interconnect Technology, (5 September 1997); doi: 10.1117/12.284660
Show Author Affiliations
Tina A. Petersen-Buchheit, Intel Corp. (United States)
William R. Johannes, Intel Corp. (United States)
Divyesh N. Patel, Intel Corp. (United States)
Jeffrey F. Coleman, Intel Corp. (United States)


Published in SPIE Proceedings Vol. 3214:
Multilevel Interconnect Technology
Divyesh N. Patel; Mart Graef, Editor(s)

© SPIE. Terms of Use
Back to Top