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Proceedings Paper

Line length dependencies in interconnect optimization
Author(s): Daniel Kadoch; Michael Duane; Yohan Lee
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Paper Abstract

Metal line delay has become increasingly important for ULSI devices. Numerous expressions and software tools have been developed to describe interconnect delay as a function of the geometry and layout. Although many of these formulas have line length effects, this has not been explored in depth. Most software tools are either geared towards circuit designers, or involve more complex and CPU-intensive 3D modeling. In this work, PISCES (a 2D device simulator) was used to extract metal capacitance per unit length. We extend this approach for various lengths by creating a ladder network of the RC components and simulating in SPICE, or using simple closed-form Elmore delay equations. A new key result is that there are optimum metal line width/space for a fixed pitch and height/space ratios that are metal length dependent. For metal lines shorter than about 1500 micrometers , it is better to have narrower metal lines, and for lengths less than 500 micrometers , shrinking metal height is desirable because the penalty in resistance is more than compensated by the decrease in capacitance. For longer lines, the time delay is dominated by resistance, and wider, taller lines are better. Increasing metal spacing or reducing dielectric constant were beneficial for both long and short metal lines.

Paper Details

Date Published: 5 September 1997
PDF: 8 pages
Proc. SPIE 3214, Multilevel Interconnect Technology, (5 September 1997); doi: 10.1117/12.284657
Show Author Affiliations
Daniel Kadoch, Advanced Micro Devices, Inc. (United States)
Michael Duane, Advanced Micro Devices, Inc. (United States)
Yohan Lee, Advanced Micro Devices, Inc. (United States)

Published in SPIE Proceedings Vol. 3214:
Multilevel Interconnect Technology
Divyesh N. Patel; Mart Graef, Editor(s)

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