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Proceedings Paper

Characterization of high-density plasma CVD USG film
Author(s): Wei Lu; Jia Zhen Zheng; John Sudijuno; Hoon Lian Yap; Kok Seng Fam; Catherine Leong; Marvin D. Liao; Yih Shung Lin
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Paper Abstract

The HDP-CVD oxide deposition process has been fully investigated with the change of gas flow and RF power up to +/- 20%. The film quality is very stable with a wet etch rate ratio (WERR) of 1.5 relative to thermal oxide. The uniformity for both sputter and deposition are all below 3%, and the D/S ratio is only sensitively affected by bias RF power and side SiH4 flow. Three important factors, namely bias-RF, backside He flow and O2/SiH4 ratio, which affect strongly on the film quality, are studied in detail by measurement of film refractive index, stress, water absorption, WERR, and by pressure cook test (PCT). Lower backside He pressure as well as higher bias-RF power result in higher wafer temperature and better film quality. After PCT, the films do not show any increase in the silanol content and WERR. A liner process with lower bias-RF power is discussed to protect corner sputtering and plasma charging.

Paper Details

Date Published: 5 September 1997
PDF: 10 pages
Proc. SPIE 3214, Multilevel Interconnect Technology, (5 September 1997); doi: 10.1117/12.284655
Show Author Affiliations
Wei Lu, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Jia Zhen Zheng, Chartered Semiconductor Manufacturing Ltd. (Singapore)
John Sudijuno, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Hoon Lian Yap, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Kok Seng Fam, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Catherine Leong, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Marvin D. Liao, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Yih Shung Lin, Chartered Semiconductor Manufacturing Ltd. (Singapore)


Published in SPIE Proceedings Vol. 3214:
Multilevel Interconnect Technology
Divyesh N. Patel; Mart Graef, Editor(s)

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