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Proceedings Paper

Optimization of pre-gate clean technology for a 0.35-um dual-oxide/dual-voltage CMOS process
Author(s): Hunter B. Brugge; Martin P. Karnett; Emmanuel de Muizon; Jingrong Zhou; Allen Page; Landon B. Vines; Bradley J. Haby
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Paper Abstract

As voltages scale with device miniaturization, it is desirable to maintain dual-voltage operation for efficient system integration. While this dual-voltage approach is commonly used for CMOS EEPROM circuits, its use in an ASIC environment is relatively new. The effects of pre-gate clean processing technology on oxide integrity were investigated for both low (3.3 V) and high (5 V) voltage gate oxides in a 0.35 micrometer triple level metal CMOS process with dual gate oxide. Significant improvements in the high-voltage gate oxide quality were realized by reducing the temperature of the pre- gate SC1 (NH4OH/H2O2/H2O) cleaning solution and by minimizing the exposure time of the high-voltage gate oxide to HF. Also, addition of HCl to dilute HF as the final step in the pre-gate cleaning improved the high-voltage gate oxide quality. These improvements to the high-voltage gate oxide quality were achieved without compromising the quality of the low-voltage gate oxide.

Paper Details

Date Published: 27 August 1997
PDF: 9 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284619
Show Author Affiliations
Hunter B. Brugge, VLSI Technology, Inc. (United States)
Martin P. Karnett, VLSI Technology, Inc. (United States)
Emmanuel de Muizon, VLSI Technology, Inc. (United States)
Jingrong Zhou, VLSI Technology, Inc. (United States)
Allen Page, VLSI Technology, Inc. (United States)
Landon B. Vines, VLSI Technology, Inc. (United States)
Bradley J. Haby, VLSI Technology, Inc. (United States)

Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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