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Proceedings Paper

Silicon bipolar transistor scaling for advanced BiCMOS SRAM applications
Author(s): H. Tian; Asanga H. Perera; D. O'Meara; H. De; C. K. Subramanian; P. Rehmann; James D. Hayden; Norm Herr
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Paper Abstract

In this paper, we discuss scaled silicon bipolar transistor performance for advanced BiCMOS SRAM applications. In particular, we present experimental results of non-self aligned, single poly emitter bipolar transistors with critical dimensions scaled vertically and laterally. We demonstrate the device performance enhancement by properly scaling and show device design tradeoffs with key bipolar device parameters.

Paper Details

Date Published: 27 August 1997
PDF: 10 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284616
Show Author Affiliations
H. Tian, Motorola (United States)
Asanga H. Perera, Motorola (United States)
D. O'Meara, Motorola (United States)
H. De, Motorola (United States)
C. K. Subramanian, Motorola (United States)
P. Rehmann, Motorola (United States)
James D. Hayden, Motorola (United States)
Norm Herr, Motorola (United States)

Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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