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Proceedings Paper

SiGe/Si vertical PMOSFET device design and fabrication
Author(s): Kou Chen Liu; Sandeep K. Oswal; Samit K. Ray; Sanjay K. Banerjee
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Paper Abstract

As channel lengths shrink continuously to smaller dimensions in order to improve performance and packing density, lithography, isolation, power supply and short channel effects have proved to be major limitations. Recently vertical MOSFETs (VMOS), also known as surround gate transistors, or 3-D side- wall transistors have been shown to overcome these process limitations. In this paper, we review the various VMOS technologies and applications and compare the performance of these devices to planar devices. We also present a novel deep submicron vertical SiGe/Si PMOSFET fabricated by Ge implantation. The Ge was implanted in the Si vertical channel to form a strained SiGe layer to increase drive current in P channel devices. PMOS drive current can be increased by about 100% compared to Si control devices. Thus, this technology offers CMOS circuit designers the flexibility to match PMOS and NMOS current drive capabilities, which was previously limited by the difference in electron and hole mobilities in Si.

Paper Details

Date Published: 27 August 1997
PDF: 6 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284608
Show Author Affiliations
Kou Chen Liu, Univ. of Texas at Austin (United States)
Sandeep K. Oswal, Univ. of Texas at Austin (United States)
Samit K. Ray, Indian Institute of Technology (India)
Sanjay K. Banerjee, Univ. of Texas at Austin (United States)


Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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