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Proceedings Paper

Improvement of edge leakage in PBL-isolated SOI NMOSFETs
Author(s): David Burnett; Mitch Lien; Kelly Baker
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Paper Abstract

One of the major problems for SOI technologies with LOCOS- based isolation is the high subthreshold leakage current along the field edge of NMOS devices. Partially depleted SOI transistors with a modified poly-buffered LOCOS isolation show a high off-leakage for devices with a silicon thickness of 900 angstroms and a gate oxide thickness of 105 angstroms due to the low threshold voltage of the parasitic edge device. The off-leakage is reduced by two orders of magnitude by increasing the doping of the edge device by using either a retrograde well or a lower temperature ILD0 reflow cycle. A further improvement in the off-leakage is observed by thinning the gate oxide thickness to 90 angstroms while increasing the channel doping to maintain a similar threshold voltage. The edge device is also shown to be very sensitive to the silicon film thickness. For the same channel implants and gate oxide thickness, an increase in the silicon thickness from 900 to 1100 angstroms eliminates the edge device resulting in excellent subthreshold characteristics.

Paper Details

Date Published: 27 August 1997
PDF: 10 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284598
Show Author Affiliations
David Burnett, Motorola (United States)
Mitch Lien, Motorola (United States)
Kelly Baker, Motorola (United States)

Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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