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Proceedings Paper

Impact of photoresist taper and implant tilt angle on the interwell isolation of subquarter-micron CMOS technologies
Author(s): Percy V. Gilbert; John Grant; Paul Tsui; Charles Fredrick King; William J. Taylor; Karl Wimmer
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Paper Abstract

The impact of photoresist taper and implant tilt angle on the interwell isolation of a sub-0.25 micrometer CMOS technology is investigated. It is shown that as the trench depth is decreased and the n-well dose and energy is increased, interwell isolation below 1 micron N+/P+ spacing is degraded. The reduction of photoresist taper is shown to be a key factor in improving interwell isolation and decreasing MOSFET device parasitics. By optimizing the photoresist process to minimize taper, acceptable N+/P+ isolation is achieved down to 0.7 micrometers. Also, by utilizing a two dimensional interwell isolation test structure, it is found for the first time that as the interwell isolation is scaled into the sub-micron regime, lateral n-well dopant displacement caused by the implant tilt angle can result in reduced overlay margin.

Paper Details

Date Published: 27 August 1997
PDF: 8 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284596
Show Author Affiliations
Percy V. Gilbert, Motorola, Inc. (United States)
John Grant, Motorola, Inc. (United States)
Paul Tsui, Motorola, Inc. (United States)
Charles Fredrick King, Motorola, Inc. (United States)
William J. Taylor, Motorola, Inc. (United States)
Karl Wimmer, Motorola, Inc. (United States)


Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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