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Proceedings Paper

Prediction of CMOS transistor performance at 0.10-um gate length using tuned simulations
Author(s): S. Sridhar; Manoj Mehrotra; Mark Rodder; Mahalingam Nandakumar; Ih-Chin Chen
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Paper Abstract

Predictive device simulation is essential in order to improve MOSFET design, and reduce development time and costs. In this paper, the results of a simulation study carried out to predict the performance of N and P channel MOSFETs having a physical gate length of 0.10 micrometer at supply voltages of 1.2 and 1.5 V are presented. The study was used to determine the feasibility of the FOM goal for scaled 0.10 micrometer CMOS, and to identify the values of key device parameters [the external source drain resistance (Rext), poly-gate doping, etc.] which would improve device performance.

Paper Details

Date Published: 27 August 1997
PDF: 12 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284594
Show Author Affiliations
S. Sridhar, Texas Instruments Inc. (United States)
Manoj Mehrotra, Texas Instruments Inc. (United States)
Mark Rodder, Texas Instruments Inc. (United States)
Mahalingam Nandakumar, Texas Instruments Inc. (United States)
Ih-Chin Chen, Texas Instruments Inc. (United States)

Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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