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Proceedings Paper

Characterization of Vth fluctuation in 0.15-um n-MOSFETs for gigabit DRAM cell transistors
Author(s): Toshihiko Miyashita; Hiroshi Suzuki; Manabu Kojima; Yasuo Nara; Nobuo Sasaki
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Paper Abstract

This paper presents a study of threshold voltage (Vth) fluctuation in n-MOSFETs having both gate lengths (Lg) and widths (W) as small as 0.15 micrometer for giga-bit DRAM cell transistors. The effects of varying Lg, W, and the gate oxide thickness (Tox) and fluctuation in the concentration of channel impurities (Na) were studied in detail. We fabricated and evaluated n-MOSFETs having various sizes of Lg and W. The Vth and the Vth fluctuation of these devices, when Lg/W equals 0.14/0.15 micrometer and the channel implantation condition was B+, 10 keV, and 9E12 cm-2, were 0.33 V and 47 mV, respectively. A short- channel effect and a slight inverse narrow-width effect were also observed. By determining the origin of the Vth fluctuation, we found that the short- and narrow-channel effect (combined with variations in device dimensions) had only a minor effect on Vth fluctuations at higher channel impurity concentrations, and that the channel impurity fluctuation had the biggest influence. This channel impurity fluctuation cannot be explained simply by the statistical dopant fluctuation. We presume that anomalous impurity diffusion, such as transient enhanced diffusion (TED), during the gate oxidation process may be the dominant factor.

Paper Details

Date Published: 27 August 1997
PDF: 8 pages
Proc. SPIE 3212, Microelectronic Device Technology, (27 August 1997); doi: 10.1117/12.284589
Show Author Affiliations
Toshihiko Miyashita, Fujitsu Labs. Ltd. (Japan)
Hiroshi Suzuki, Fujitsu Labs. Ltd. (Japan)
Manabu Kojima, Fujitsu Labs. Ltd. (Japan)
Yasuo Nara, Fujitsu Labs. Ltd. (Japan)
Nobuo Sasaki, Fujitsu Labs. Ltd. (Japan)

Published in SPIE Proceedings Vol. 3212:
Microelectronic Device Technology
Mark Rodder; Toshiaki Tsuchiya; David Burnett; Dirk Wristers, Editor(s)

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