Share Email Print
cover

Proceedings Paper

Real-time image reconstructor ASIC
Author(s): Carlos Augusto Paiva da Silva Martins; Joao Antonio Zuffo; Sergio Takeo Kofuji
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This paper shows an architectural proposal for an application specific integrated circuit (ASIC) designed to perform image reconstruction in real time. This architecture implements in hardware the reconstruction technique, called 2D normalized sampled finite sinc reconstructor (NSFSR 2D), which has been formerly proposed and implemented in software. We develop an ASIC that implements NSFSR 2D technique as a dedicated static pipeline architecture. We model and simulate this architecture using VHDL hardware description language. Based on analysis of the validation results, we conclude that the proposed architecture implements the NSFSR 2D correctly and is optimized in performance when compared with a software-based implementation.

Paper Details

Date Published: 22 July 1997
PDF: 11 pages
Proc. SPIE 3074, Visual Information Processing VI, (22 July 1997); doi: 10.1117/12.280629
Show Author Affiliations
Carlos Augusto Paiva da Silva Martins, Univ. de Sao Paolo and Pontificia Univ. Catolica de Minas Gerais (Brazil)
Joao Antonio Zuffo, Univ. de Sao Paolo (Brazil)
Sergio Takeo Kofuji, Univ. de Sao Paolo (Brazil)


Published in SPIE Proceedings Vol. 3074:
Visual Information Processing VI
Stephen K. Park; Richard D. Juday, Editor(s)

© SPIE. Terms of Use
Back to Top