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Proceedings Paper

Transmission electron microscopy of defects in NMOS and PMOS structures
Author(s): Antony J. Bourdillon; Yew G. Koh; Shu L. Chiang; Chong Wee Lim; Jong Ren Kong; Cao Guobing
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Paper Abstract

Decreasing dimensions in integrated circuits impose increasing demands in processing. Among requirements are reduced resistance in interconnects on high density chips and also low leakage currents. Transmission electron microscopy has been used to study the microstructures associated with salicide interconnects in wafers prepared on design rules between 0.6 to 0.35 microns. Irregularities such as varying gate width, interconnects in wafers prepared on design rules between 0.6 to 0.35 microns. Irregularities such as varying gate width, intergrowths of poly-silicon and polycrystallinity in titanium silicide were observed. Precipitation has not so far been noticed in pure or doped silica insulating layers.

Paper Details

Date Published: 14 August 1997
PDF: 7 pages
Proc. SPIE 3183, Microlithographic Techniques in IC Fabrication, (14 August 1997); doi: 10.1117/12.280546
Show Author Affiliations
Antony J. Bourdillon, National Univ. of Singapore (Singapore)
Yew G. Koh, National Univ. of Singapore (Singapore)
Shu L. Chiang, National Univ. of Singapore (Singapore)
Chong Wee Lim, National Univ. of Singapore (Singapore)
Jong Ren Kong, National Univ. of Singapore (Singapore)
Cao Guobing, Singapore Productivity and Standards Board (Singapore)


Published in SPIE Proceedings Vol. 3183:
Microlithographic Techniques in IC Fabrication
Soon Fatt Yoon; Raymond Yu; Chris A. Mack, Editor(s)

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