Share Email Print
cover

Proceedings Paper

Resist profile and CD control improvement by using optimized resist thickness and substrate film stack ratio for 0.35-um logic process
Author(s): Ming Hui Fan; Raymond Yu; Ronfu Chu; Chet Ping Lim
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

LOCOS is the most widely used method for 0.35 micrometers process isolation. 2000 angstrom silicon nitride on 200 angstrom padoxide was selected as oxidation barrier before process optimization for the need of control the bird's beak and stress which affects the subsequent gate oxide quality. However, resist profile is prone to footing at this film stack. Severe footing could make minimum space CD too small, even not opened, to cause isolation failure. Experiment data shows that if nitride thickness varies from 1.9 K to 2.1 K, line CD variation can be up to 0.08 micrometers for a 0.6 micrometers line, which is about 80 percent of CD variation budget. Based on simulation results, 8 different nitride thickness in the range of 1750 angstrom to 2100 angstrom with step of 50 angstrom were deposited on 200 angstrom padoxide. Swing curve, CD versus nitride thickness for resist Emax and Emin, CD versus different exposure dose charts were obtained. Resist profile cross-sectional SEM pictures were also done to confirm simulation and in-line CD SEM measurement. An optimum combination of substrate film stack and resist thickness was selected. After implementation of this optimization, the sensitivity of CD to the nitride thickness was greatly reduced. Better resist profile and CD control were obtained. This was well confirmed by in-line monitoring data.

Paper Details

Date Published: 14 August 1997
PDF: 10 pages
Proc. SPIE 3183, Microlithographic Techniques in IC Fabrication, (14 August 1997); doi: 10.1117/12.280545
Show Author Affiliations
Ming Hui Fan, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Raymond Yu, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Ronfu Chu, Chartered Semiconductor Manufacturing Ltd. (Singapore)
Chet Ping Lim, Chartered Semiconductor Manufacturing Ltd. (Singapore)


Published in SPIE Proceedings Vol. 3183:
Microlithographic Techniques in IC Fabrication
Soon Fatt Yoon; Raymond Yu; Chris A. Mack, Editor(s)

© SPIE. Terms of Use
Back to Top