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Proceedings Paper

Associative architecture for image processing
Author(s): Rutie Adar; Avidan Akerib
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Paper Abstract

This article presents a new generation in parallel processing architecture for real-time image processing. The approach is implemented in a real time image processor chip, called the XiumTM-2, based on combining a fully associative array which provides the parallel engine with a serial RISC core on the same die. The architecture is fully programmable and can be programmed to implement a wide range of color image processing, computer vision and media processing functions in real time. The associative part of the chip is based on patented pending methodology of Associative Computing Ltd. (ACL), which condenses 2048 associative processors, each of 128 'intelligent' bits. Each bit can be a processing bit or a memory bit. At only 33 MHz and 0.6 micron manufacturing technology process, the chip has a computational power of 3 billion ALU operations per second and 66 billion string search operations per second. The fully programmable nature of the XiumTM-2 chip enables developers to use ACL tools to write their own proprietary algorithms combined with existing image processing and analysis functions from ACL's extended set of libraries.

Paper Details

Date Published: 19 September 1997
PDF: 9 pages
Proc. SPIE 3166, Parallel and Distributed Methods for Image Processing, (19 September 1997); doi: 10.1117/12.279621
Show Author Affiliations
Rutie Adar, Associative Computing Ltd. (Israel)
Avidan Akerib, Associative Computing Ltd. (Israel)

Published in SPIE Proceedings Vol. 3166:
Parallel and Distributed Methods for Image Processing
Hongchi Shi; Patrick C. Coffield, Editor(s)

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