Share Email Print
cover

Proceedings Paper

Reconfigurable-hardware-based digital signal processing for wireless communications
Author(s): Kevin J. Page; Jeanette F. Arrigo; Paul M. Chau
Format Member Price Non-Member Price
PDF $17.00 $21.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper presents, index mapping, a technique to efficiently map a widely used class of digital signal processing algorithms onto a space/time paradigm with immediate representation as the partitioning and scheduling map of a small, I/O efficient, hardware array. When applied to reconfigurable FPGA based hardware architectures with downstream sea-of-gates optimization methods, the resulting systems form a dynamic signal processing environment with the best mix of performance and flexibility for wireless applications. Herein, index mapping is demonstrated with a mapping of the fast Fourier transform (FFT) onto an FPGA computing machine, the reconfigurable processor (RCP).

Paper Details

Date Published: 24 October 1997
PDF: 12 pages
Proc. SPIE 3162, Advanced Signal Processing: Algorithms, Architectures, and Implementations VII, (24 October 1997); doi: 10.1117/12.279508
Show Author Affiliations
Kevin J. Page, Univ. of California/San Diego (United States)
Jeanette F. Arrigo, Univ. of California/San Diego (United States)
Paul M. Chau, Univ. of California/San Diego (United States)


Published in SPIE Proceedings Vol. 3162:
Advanced Signal Processing: Algorithms, Architectures, and Implementations VII
Franklin T. Luk, Editor(s)

© SPIE. Terms of Use
Back to Top