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Proceedings Paper

Design and tuning of FPGA implementations of neural networks
Author(s): Peter J. C. Clare; J. W. Gulley; Duncan Hickman; Moira I. Smith
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Paper Abstract

Artificial neural network (ANN) algorithms are applicable in a variety of roles for image processing in infrared search and track (IRST) systems. Achieving a high throughput is a key objective in developing ANNs for processing large numbers of pixels at high frame rates. Previous work has investigated the use of a neural core supported by configurable logic to achieve a versatile technology applicable to a variety of systems. The implementation of multi-layer perceptron (MLP) ANNs, using field programmable gate array (FPGA) technology to ensure upgradability and reconfigurability, is the focus of this research. Approximations to the MLP algorithms are needed to ensure that a high throughput can be achieved with a sufficiently low gate count.

Paper Details

Date Published: 23 June 1997
PDF: 8 pages
Proc. SPIE 3069, Automatic Target Recognition VII, (23 June 1997); doi: 10.1117/12.277097
Show Author Affiliations
Peter J. C. Clare, Central Research Labs. Ltd. (United Kingdom)
J. W. Gulley, Central Research Labs. Ltd. (United Kingdom)
Duncan Hickman, Pilkington Optronics (United Kingdom)
Moira I. Smith, Pilkington Optronics (United Kingdom)


Published in SPIE Proceedings Vol. 3069:
Automatic Target Recognition VII
Firooz A. Sadjadi, Editor(s)

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