Share Email Print
cover

Proceedings Paper

Design and implementation of digital controllers for smart structures using field-programmable gate arrays
Author(s): Jamie S. Kelly; Hiroshi Clifford Bowman; Vittal S. Rao; Hardy Joseph Pottinger
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Implementation issues represent an unfamiliar challenge to most control engineers, and many techniques for controller design ignore these issues outright. Consequently, the design of controllers for smart structural systems usually proceeds without regard for their eventual implementation, thus resulting either in serious performance degradation or in hardware requirements that squander power, complicate integration, and drive up cost. The level of integration assumed by the Smart Patch further exacerbates these difficulties, and any design inefficiency may render the realization of a single-package sensor-controller-actuator system infeasible. The goal of this research is to automate the controller implementation process and to relieve the design engineer of implementation concerns like quantization, computational efficiency, and device selection. We specifically target Field Programmable Gate Arrays (FPGAs) as our hardware platform because these devices are highly flexible, power efficient, and reprogrammable. The current study develops an automated implementation sequence that minimizes hardware requirements while maintaining controller performance. Beginning with a state space representation of the controller, the sequence automatically generates a configuration bitstream for a suitable FPGA implementation. MATLAB functions optimize and simulate the control algorithm before translating it into the VHSIC hardware description language. These functions improve power efficiency and simplify integration in the final implementation by performing a linear transformation that renders the controller computationally friendly. The transformation favors sparse matrices in order to reduce multiply operations and the hardware necessary to support them; simultaneously, the remaining matrix elements take on values that minimize limit cycles and parameter sensitivity. The proposed controller design methodology is implemented on a simple cantilever beam test structure using FPGA hardware. The experimental closed loop response is compared with that of an automated FPGA controller implementation. Finally, we explore the integration of FPGA based controllers into a multi-chip module, which we believe represents the next step towards the realization of the Smart Patch.

Paper Details

Date Published: 19 June 1997
PDF: 12 pages
Proc. SPIE 3046, Smart Structures and Materials 1997: Smart Electronics and MEMS, (19 June 1997); doi: 10.1117/12.276620
Show Author Affiliations
Jamie S. Kelly, Univ. of Missouri/Rolla (United States)
Hiroshi Clifford Bowman, Univ. of Missouri/Rolla (United States)
Vittal S. Rao, Univ. of Missouri/Rolla (United States)
Hardy Joseph Pottinger, Univ. of Missouri/Rolla (United States)


Published in SPIE Proceedings Vol. 3046:
Smart Structures and Materials 1997: Smart Electronics and MEMS
Vijay K. Varadan; Paul J. McWhorter, Editor(s)

© SPIE. Terms of Use
Back to Top