Share Email Print

Proceedings Paper

Clock multiplier with a range up to 370 MHz for video/display signal processing
Author(s): Rida Hamza
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

This paper describes the design of a clock generation circuitry to be used as part of an affordable gigabit module head mounted display. A self-calibrated tapped delay line is used to generate different clock signals, which are then passed through logical function to produce an integral- multiple of an input clock. The system is fabricated on 0.8 micrometers CMOS triple layer using MOSIS CMOS process. All processes technology can operate at 3.3 V or 5.0 V. Experimental results show a realization of 4 times clock multiplier circuit with an output range of up to 370 MHz with almost zero-clock skew. The proposed clock multiplier circuitry is simple, temperature independent, uses a very small number of transistors and hence requires less area and power dissipation than earlier realizations.

Paper Details

Date Published: 19 June 1997
PDF: 5 pages
Proc. SPIE 3046, Smart Structures and Materials 1997: Smart Electronics and MEMS, (19 June 1997); doi: 10.1117/12.276599
Show Author Affiliations
Rida Hamza, Honeywell Technology Ctr. (United States)

Published in SPIE Proceedings Vol. 3046:
Smart Structures and Materials 1997: Smart Electronics and MEMS
Vijay K. Varadan; Paul J. McWhorter, Editor(s)

© SPIE. Terms of Use
Back to Top