Share Email Print
cover

Proceedings Paper

Optimizing in-line defect monitoring using correlation with electrical failures
Author(s): Prashant A. Aji; Arnaud Lanier
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This paper describes the work done for optimization of product wafer inline monitoring using the KLA 2132 and Tencor 7700 at the SGS Thomson Rousset facility using electrical bitmapping as response. Emphasis was placed on understanding each system's capability and limitation with regards to detecting 'killer defects', as applied to different process steps. In addition speed of detection as well as signal to noise ratio were used as criteria for selecting the monitoring equipment for certain critical process steps. This experiment was carried out using a high volume product with a ROM code which made up 55 percent of the chip. The inspection was concentrated in detecting defects in this ROM area and then correlating these defects to bitmap failures.

Paper Details

Date Published: 7 July 1997
PDF: 8 pages
Proc. SPIE 3050, Metrology, Inspection, and Process Control for Microlithography XI, (7 July 1997); doi: 10.1117/12.275925
Show Author Affiliations
Prashant A. Aji, SGS-Thomson Microelectronics (France)
Arnaud Lanier, SGS-Thomson Microelectronics (France)


Published in SPIE Proceedings Vol. 3050:
Metrology, Inspection, and Process Control for Microlithography XI
Susan K. Jones, Editor(s)

© SPIE. Terms of Use
Back to Top