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Proceedings Paper

Processor arrays with asynchronous TDM optical buses
Author(s): Y. Li; S. Q. Zheng
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Paper Abstract

We propose a pipelined asynchronous time division multiplexing optical bus. Such a bus can use one of the two hardwared priority schemes, the linear priority scheme and the round-robin priority scheme. Our simulation results show that the performances of our proposed buses are significantly better than the performances of known pipelined synchronous time division multiplexing optical buses. We also propose a class of processor arrays connected by pipelined asynchronous time division multiplexing optical buses. We claim that our proposed processor array not only have better performance, but also have better scalabilities than the existing processor arrays connected by pipelined synchronous time division multiplexing optical buses.

Paper Details

Date Published: 4 April 1997
PDF: 12 pages
Proc. SPIE 3005, Optoelectronic Interconnects and Packaging IV, (4 April 1997); doi: 10.1117/12.271100
Show Author Affiliations
Y. Li, Louisiana State Univ. (United States)
S. Q. Zheng, Louisiana State Univ. (United States)


Published in SPIE Proceedings Vol. 3005:
Optoelectronic Interconnects and Packaging IV
Ray T. Chen; Peter S. Guilfoyle, Editor(s)

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