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Proceedings Paper

Effect of a silicon interlayer in low-temperature poly-SiGe thin film transistors
Author(s): Albert W. Wang; Krishna C. Saraswat
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Paper Abstract

Polycrystalline silicon-germanium TFT technology has potential for flat panel display applications because of its reduced thermal budget. Previously, single-crystal SiGe MOSFETs have used a silicon cap or interlayer between the gate oxide and the channel to improve the gate oxide interface and device performance. Here the use of a Si interlayer, ranging from 0 to 100 angstrom in thickness, in poly-SiGe TFTs fabricated by a low-temperature process is investigated. It is found that performance is significantly affected by the presence of the interlayer. The changes are due to the improvement of the SiO2-SiGe interface and the division of the drain current among the Si interlayer and SiGe film, which have different electrical properties. NMOS mobility peaks at 36 cm2/Vs with a 50 angstrom interlayer, as compared to 22 cm$_2)/Vs without an interlayer and 28 cm2/Vs in a pure Si device. Other NMOS performance parameters improve as the interlayer thickness increase.In contrast, PMOS performance initially improves when the interlayer is introduced, but then declines as the interlayer thickness increases.

Paper Details

Date Published: 10 April 1997
PDF: 8 pages
Proc. SPIE 3014, Active Matrix Liquid Crystal Displays Technology and Applications, (10 April 1997); doi: 10.1117/12.270288
Show Author Affiliations
Albert W. Wang, Stanford Univ. (United States)
Krishna C. Saraswat, Stanford Univ. (United States)

Published in SPIE Proceedings Vol. 3014:
Active Matrix Liquid Crystal Displays Technology and Applications
Tolis Voutsas; Tsu-Jae King, Editor(s)

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