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Proceedings Paper

Fractal engine
Author(s): Omid Fatemi; Sethuraman Panchanathan
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Paper Abstract

Visual media processing is becoming increasingly important because of the wide variety of image and video based applications. Recently, several architectures have been reported in the literature to implement image and video processing algorithms. They range from programmable DSP processors to application specific integrated circuits (ASICs). DSPs have to be software programed to execute individual operations in image and video processing. However they are not suitable for real-time execution of highly compute intensive applications such as fractal block processing (FBP). On the other hand, dedicated architectures and ASICs are designed to implement specific functions. Since they are optimized for a specific task, they cannot be used in a wide variety of applications. In this paper, we propose a parallel and pipelined architecture called fractal engine to implement the operations in FBP. Fractal engine is simple, modular, scaleable and is optimized to execute both low level and mid level operations. We note that implementation of the basic operations by fractal engine enables efficient execution of a majority of visual computing tasks. These include spatial filtering, contrast enhancement, frequency domain operations, histogram calculation, geometric transforms, indexing, vector quantization, fractal block coding, motion estimation, etc. The individual modules of fractal engine have been implemented in VHDL (VHSIC hardware description language). We have chosen to demonstrate the real-time execution capability of fractal engine by mapping a fractal block coding (FBC) algorithm onto the proposed architecture.

Paper Details

Date Published: 17 January 1997
PDF: 12 pages
Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); doi: 10.1117/12.263529
Show Author Affiliations
Omid Fatemi, Univ. of Ottawa (Canada)
Sethuraman Panchanathan, Univ. of Ottawa (Canada)


Published in SPIE Proceedings Vol. 3021:
Multimedia Hardware Architectures 1997
Sethuraman Panchanathan; Frans Sijstermans, Editor(s)

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