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Proceedings Paper

Clock synchronization in software MPEG-2 decoder
Author(s): Victor Ramamoorthy
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Paper Abstract

A novel design to the problem of clock synchronization in software MPEG-2 decoders is presented. A software MPEG decoder is attractive in terms of cost and performance. However a software decoder is prone to timing uncertainty and delay jitters. By a clever use of adaptive filtering and sub sampling of time stamps, a frequency locked loop can be designed to deliver almost instantaneous capture of the unknown encoder clock frequency and with high tolerance to delay jitter. The exact analysis of the system is complex. By invoking suitable approximations, a complete design methodology is derived. Computer simulations verify the design approach illustrated.

Paper Details

Date Published: 17 January 1997
PDF: 17 pages
Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); doi: 10.1117/12.263513
Show Author Affiliations
Victor Ramamoorthy, Adaptive Media Technologies (United States)

Published in SPIE Proceedings Vol. 3021:
Multimedia Hardware Architectures 1997
Sethuraman Panchanathan; Frans Sijstermans, Editor(s)

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