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Proceedings Paper

New architecture for MPEG-2 real-time encoding
Author(s): Mansour Zuair; Dikran S. Meliksetian; C. Y. Roger Chen
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Paper Abstract

A new architecture for real-time MPEG-2 encoding/decoding is presented in this paper. This architecture is based on an array of TI MVPs. The main feature of this architecture is its programmability. The inherent parallelism of the MPEG-2 algorithm is investigated in order to map it to the processor array. An I/O algorithm for the major encoding function, motion estimation, is developed to demonstrate the possibility of overlapping processing and I/O.

Paper Details

Date Published: 17 January 1997
PDF: 12 pages
Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); doi: 10.1117/12.263510
Show Author Affiliations
Mansour Zuair, Syracuse Univ. (United States)
Dikran S. Meliksetian, Syracuse Univ. (United States)
C. Y. Roger Chen, Syracuse Univ. (United States)


Published in SPIE Proceedings Vol. 3021:
Multimedia Hardware Architectures 1997
Sethuraman Panchanathan; Frans Sijstermans, Editor(s)

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