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Proceedings Paper

Architecture of a flexible real-time video encoder/decoder: the DECchip 21230
Author(s): Matthew Adiletta; Debra Bernstein; Joel Emer; Samuel Ho; William Wheeler
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Paper Abstract

Compression of video data is a highly compute-intensive activity consisting of both regular vector-style computations and general algorithmic computations. Furthermore, the conventional compression algorithms allow the encoder some degrees of freedom in the encode process, where picture quality and degree of compression can be traded off for amount of computation. These characteristics have led to a variety of approaches to video encoding. At one extreme, real-time compression can be achieved through the use of high performance vector and general purpose co- processors to generate high compression ratios and high quality. At the other end of the spectrum, compression can be performed in real-time quite easily by doing minimal analysis of the picture to enhance quality or improve compression. The DECchip 21230 strikes a compromise between these two extremes by supporting the regular vector-style computations on an inexpensive co-processor chip, but does most of the general algorithmic computation on the host CPU. This partitioning leads to a number of scheduling and buffering challenges that are addressed by a novel decomposition of the encoding process.

Paper Details

Date Published: 17 January 1997
PDF: 13 pages
Proc. SPIE 3021, Multimedia Hardware Architectures 1997, (17 January 1997); doi: 10.1117/12.263507
Show Author Affiliations
Matthew Adiletta, Digital Equipment Corp. (United States)
Debra Bernstein, Digital Equipment Corp. (United States)
Joel Emer, Digital Equipment Corp. (United States)
Samuel Ho, Digital Equipment Corp. (United States)
William Wheeler, Digital Equipment Corp. (United States)


Published in SPIE Proceedings Vol. 3021:
Multimedia Hardware Architectures 1997
Sethuraman Panchanathan; Frans Sijstermans, Editor(s)

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