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Proceedings Paper

Software to support logic synthesis from behavioral specifications
Author(s): Clarindo I.P.S. Padua
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Paper Abstract

A logic synthesis package (LSP) is presented in connection with a method for generation of a logic specification from a behavioral description of a digital circuit. LSP is designed to be attached to a silicon compiler, providing a series of primitives which support typical logical synthesis operations like translation into a lower level form, verification, and minimization. The method was applied to the BELA compiler, a FSM (Finite State Machine) synthesizer tool. For the purpose of presentation, the logic synthesis method was divided into two parts. The first part involves synthesis of purely combinational logic. The second part concerns verification, the extraction of a functional form from the input description and involves sequencing. This paper covers the fist part of the synthesis method. A future paper, using the concepts developed here, shall present the second part of the synthesis method.

Paper Details

Date Published: 1 November 1990
PDF: 11 pages
Proc. SPIE 1405, 5th Congress of the Brazilian Society of Microelectronics, (1 November 1990); doi: 10.1117/12.26304
Show Author Affiliations
Clarindo I.P.S. Padua, UFMG (Brazil)


Published in SPIE Proceedings Vol. 1405:
5th Congress of the Brazilian Society of Microelectronics

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