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Proceedings Paper

Free programmable smart pixel processor element arrays for standard functions
Author(s): Bernd Kasche; Dietmar Fey
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Paper Abstract

The major problems in the current VLSI design are restrictions of both the number of available pins and the of-chip communication speed. The currently lasting process of increasing integration density of VLSI chips keeps these problems alive and still increases the difficulties respectively. Due to physical reasons the ability of a high speed off-chip communication in the same range of the on- chip communication is very difficult to achieve. Optoelectronic 3D circuits based on smart pixel technologies offer a principle solution for the problems mentioned above. We think for the success of optoelectronic computing it is very important to get flexible usable smart pixel circuits. Hence, we present an architecture design for programmable smart pixels. Our approach combines the functional flexibility of FPGAs with the advantages of optoelectronics providing fast and high dense optical interconnections. Moreover, this combination allows the design of various 3D processor element architectures by changing logical behavior and topology to get routing more simple and offering higher data throughput. After an overview of existing solutions we demonstrate a hardware approach of an ALU, based on a 3D free programmable SPPE array for the fast calculation of standard functions, e.g. exp, sin, cos,...furthermore we specify hardware relevant parameters.

Paper Details

Date Published: 27 December 1996
PDF: 5 pages
Proc. SPIE 2969, Second International Conference on Optical Information Processing, (27 December 1996); doi: 10.1117/12.262622
Show Author Affiliations
Bernd Kasche, Friedrich-Schiller-Univ. Jena (Germany)
Dietmar Fey, Friedrich-Schiller-Univ. Jena (Germany)


Published in SPIE Proceedings Vol. 2969:
Second International Conference on Optical Information Processing
Zhores I. Alferov; Yuri V. Gulyaev; Dennis R. Pape, Editor(s)

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