Share Email Print

Proceedings Paper

Noise degradation and fault tolerance in annealed binary-phase hologram interconnections
Author(s): Patrick J. Smith; Sergei Samus; William J. Hossack; David G. Vass
Format Member Price Non-Member Price
PDF $14.40 $18.00
cover GOOD NEWS! Your organization subscribes to the SPIE Digital Library. You may be able to download this paper for free. Check Access

Paper Abstract

Binary, computer-generated phase holograms can be displayed on a ferroelectric liquid crystal over silicon spatial light modulator to give a high-speed switchable interconnection element. However, these devices are prone to fabrication defects, including non-operational pixels, variations in the liquid crystal cell thickness and warping of the silicon backplane. We investigate the effects of these fabrication faults on hologram efficiency by modelling them in software, and test the ability of the iterative design technique to compensate for such defects. Evidence of back-plane and cell thickness faults in 256 by 256 pixel binary FLC over silicon SLMs is presented and discussed. A projected optical design scheme that removes the requirement for the mapping of defects on a particular SLM is outlined.

Paper Details

Date Published: 27 December 1996
PDF: 6 pages
Proc. SPIE 2969, Second International Conference on Optical Information Processing, (27 December 1996); doi: 10.1117/12.262601
Show Author Affiliations
Patrick J. Smith, Univ. of Edinburgh (United Kingdom)
Sergei Samus, Univ. of Edinburgh (United Kingdom)
William J. Hossack, Univ. of Edinburgh (United Kingdom)
David G. Vass, Univ. of Edinburgh (United Kingdom)

Published in SPIE Proceedings Vol. 2969:
Second International Conference on Optical Information Processing
Zhores I. Alferov; Yuri V. Gulyaev; Dennis R. Pape, Editor(s)

© SPIE. Terms of Use
Back to Top