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Proceedings Paper

CAE tools for verifying high-performance digital systems
Author(s): Lawrence M. Rubin
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Paper Abstract

The high signal density clock rates and output slew rates associated with state-of-the-art digital logic renders design verification of modern high performance digital systems to be increasingly difficult and critical. The electrical and mechanical design of these circuits must be analyzed in conjunction with the analysis and simulation of the underlying logic design to result in operational and manufacturable systems. This paper will describe several useful techniques relevant to verification of such systems including static timing verification transmission line simulation and crosstalk analysis. The principles underlying these techniques will be discussed and results for sample algorithms given.

Paper Details

Date Published: 1 April 1991
PDF: 23 pages
Proc. SPIE 1390, Microelectronic Interconnects and Packages: System and Process Integration, (1 April 1991); doi: 10.1117/12.25588
Show Author Affiliations
Lawrence M. Rubin, Quad Design Technology, Inc. (United States)


Published in SPIE Proceedings Vol. 1390:
Microelectronic Interconnects and Packages: System and Process Integration
Stuart K. Tewksbury; John R. Carruthers, Editor(s)

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