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Proceedings Paper

Polynomial-transform-based approach to computing 2D DFTs using reconfigurable computers
Author(s): Chris H. Dick; Fred J. Harris
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Paper Abstract

Considerable success has been achieved in developing signal processing algorithms that are efficient from the standpoint of number of operations. However, what is needed now is to develop new algorithms which are better adapted to existing hardware, or to device new architectures that more efficiently exploit existing signal processing algorithms. This latter approach forms the basis of this paper. An FPGA architecture is described that takes advantage of the reduced computational requirements of the polynomial transform method for computing 2-D DFTs. The performance of the architecture is presented and is shown to use 36% less FPGA resources than a row-column DFT processor. A multi-FPGA architecture is described that is capable of processing 24 512 by 512 pixel images per second. The multi-FPGA processor is 46% more area efficient than a row-column DFT implementation.

Paper Details

Date Published: 21 October 1996
PDF: 12 pages
Proc. SPIE 2914, High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic, (21 October 1996); doi: 10.1117/12.255837
Show Author Affiliations
Chris H. Dick, La Trobe Univ. (Australia)
Fred J. Harris, San Diego State Univ. (United States)


Published in SPIE Proceedings Vol. 2914:
High-Speed Computing, Digital Signal Processing, and Filtering Using Reconfigurable Logic
John Schewel; Peter M. Athanas; V. Michael Bove Jr.; John Watson, Editor(s)

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