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Proceedings Paper

Challenges of using advanced multichip packaging for next generation spaceborne computers
Author(s): Thomas J. Moravec
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Paper Abstract

The Strategic Defense Initiative and other space programs have accelerated the requirement to put fast powerful computers with large memory requirements into space on various satellites. Operation during launch and in space environments places some challenging requirements on siliconbased electronics. They must survive large thermal and mechanical shocks and exposure to radiation. This paper presents one of the approaches taken to date to build spaceborne computers with high density multi-chip packaging technology.

Paper Details

Date Published: 1 April 1991
PDF: 7 pages
Proc. SPIE 1390, Microelectronic Interconnects and Packages: System and Process Integration, (1 April 1991); doi: 10.1117/12.25576
Show Author Affiliations
Thomas J. Moravec, Honeywell, Inc. (United States)


Published in SPIE Proceedings Vol. 1390:
Microelectronic Interconnects and Packages: System and Process Integration
Stuart K. Tewksbury; John R. Carruthers, Editor(s)

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