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Proceedings Paper

Embedded-processor architecture for parallel DSP algorithms
Author(s): Rick F. Hobson; Peter S. Wong; S. A. Evenson
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Paper Abstract

A methodology for constructing parallel embedded DSP systems is described. The method uses a software and embedded processor abstraction to help raise the level of problem analysis above the raw state machine concept. Custom architectures are constructed by using multiple copies of a core embedded processor linked together with FIFO memories or other communication structures, and augmented with appropriate high speed data manipulation IO devices. Some field programmability and customization is possible through the use of SRAM program memories.

Paper Details

Date Published: 22 October 1996
PDF: 11 pages
Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); doi: 10.1117/12.255463
Show Author Affiliations
Rick F. Hobson, Simon Fraser Univ. (Canada)
Peter S. Wong, Simon Fraser Univ. (Canada)
S. A. Evenson, Simon Fraser Univ. (Canada)


Published in SPIE Proceedings Vol. 2846:
Advanced Signal Processing Algorithms, Architectures, and Implementations VI
Franklin T. Luk, Editor(s)

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