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Proceedings Paper

FIR filter implementation using bit-serial arithmetic and partial summation trees
Author(s): S. Gibb; P. J. W. Graumann; Laurence E. Turner
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Paper Abstract

An architecture which efficiently implements a fixed coefficient FIR filter using pipelined bit-serial arithmetic is described. A specialized multiplier decomposition exploiting multiplier coefficient similarities is used to obtain a reduced hardware area implementation. A design methodology which supports the conversion of a frequency response specification into a gate level implementation of the filter is presented. An 89 tap FIR filter meeting a multi-band frequency response specification, with 16 bit internal data precision and a sample rate of 1.6 GHz for parallel input and output data is implemented on a single XILINX 4005PG156 FPGA device.

Paper Details

Date Published: 22 October 1996
PDF: 12 pages
Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); doi: 10.1117/12.255462
Show Author Affiliations
S. Gibb, Univ. of Calgary (Canada)
P. J. W. Graumann, Univ. of Calgary (Canada)
Laurence E. Turner, Univ. of Calgary (Canada)

Published in SPIE Proceedings Vol. 2846:
Advanced Signal Processing Algorithms, Architectures, and Implementations VI
Franklin T. Luk, Editor(s)

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