Proceedings Paper
Interleaved IIR filter on Δ-Σ modulated signals| Format | Member Price | Non-Member Price |
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Paper Abstract
This paper describes a circuit implementing 12 fully independent biquad digital filters operating on (Delta) - (Sigma) modulated signals with 28 b resolution. A carry-save adder with partial carry propagation (Delta) -(Sigma) modulator is used together with a pipelined architecture that interleaves all of the filters on a single datapath. Implemented in TSPC logic, the circuit comprises 95 K transistors, including a variable frequency on-chip clock generator.
Paper Details
Date Published: 22 October 1996
PDF: 8 pages
Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); doi: 10.1117/12.255461
Published in SPIE Proceedings Vol. 2846:
Advanced Signal Processing Algorithms, Architectures, and Implementations VI
Franklin T. Luk, Editor(s)
PDF: 8 pages
Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); doi: 10.1117/12.255461
Show Author Affiliations
David M. Lewis, Univ. of Toronto (Canada)
Published in SPIE Proceedings Vol. 2846:
Advanced Signal Processing Algorithms, Architectures, and Implementations VI
Franklin T. Luk, Editor(s)
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