Share Email Print

Proceedings Paper

Novel high-speed bit-parallel multiply accumulate arithmetic architecture
Author(s): Vishwas M. Rao; Behrouz Nowrouzian
Format Member Price Non-Member Price
PDF $17.00 $21.00

Paper Abstract

This paper presents an architecture for high-speed bit- parallel multiply-accumulate arithmetic operation. This architecture employs the modified-Booth recoding algorithm for multiplication, and a kernel using mixed (sign, value)- encoded signed-binary (SB) and two's complement (TC) computation for carry-free generation of the SB partial product sums. The final SB partial product sum undergoes full-precision accumulation, rounding, and overflow correction concurrently, to facilitate a high-speed overall operation. A high-performance architecture is proposed for IEEE Standard 754 default rounding of the SB result. This architecture exploits the carry-free property of redundant number addition to perform the rounding operation, again concurrently with the multiplication and accumulation operations. The conversion of the final rounded SB number into its corresponding TC format is achieved by using a fast pipelined lookahead converter. The resulting multiply- accumulate arithmetic architecture is subsequently parameterized for ASIC implementations using the Actel 1.2 (mu) FPGA technology parameters. It is demonstrated that the use of (sign, value)-encoding leads to combined area and time efficient implementations.

Paper Details

Date Published: 22 October 1996
PDF: 13 pages
Proc. SPIE 2846, Advanced Signal Processing Algorithms, Architectures, and Implementations VI, (22 October 1996); doi: 10.1117/12.255442
Show Author Affiliations
Vishwas M. Rao, Univ. of Calgary (Canada)
Behrouz Nowrouzian, Univ. of Calgary (Canada)

Published in SPIE Proceedings Vol. 2846:
Advanced Signal Processing Algorithms, Architectures, and Implementations VI
Franklin T. Luk, Editor(s)

© SPIE. Terms of Use
Back to Top