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Proceedings Paper

Application of electrodeposition processes to advanced package fabrication
Author(s): Sol Krongelb; John O. Dukovic; M. L. Komsa; S. Mehdizadeh; Lubomyr T. Romankiw; Panayotis C. Andricacos; A. T. Pfeiffer; Kason Wong
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Paper Abstract

Conductors for advanced packaging have thicknesses of the order of 6 microns and aspect ratios that are approaching 1: 1. These requirements are well within the capabilities of electrodeposition technology. The experience of the last decade in using electrodeposition to build thin-film recording heads which have similar and in some respects even more demanding specifications than packaging structures is directly applicable to the needs of packaging. This paper will show the application of resist-pattern plating to fabricating conductors for packaging will discuss the capabilities and limitations of resist-pattern plating plating and will indicate the parameters that need to be understood and controlled for the successful application of electrodeposition technology to microelectronic structures. A multi-level package structure can be considered as a repetition of several conductor and via levels. Each conductor/via level is made by first sputter depositing a seed layer of Cr/Cu in which the Cu is of the order of 2000 A thick. A layer of photoresist is then applied over the seed layer and openings are patterned in the resist to defme the conductor pattern. Electrical contact is now made to the seed layer and the part is immersed in an electroplating solution to deposit Cu in the openings defmed by the resist pattern. The thickness of the deposit is determined by the time and current density of plating the thickness of the photoresist must slightly exceed the desired

Paper Details

Date Published: 1 April 1991
PDF: 8 pages
Proc. SPIE 1389, Microelectronic Interconnects and Packages: Optical and Electrical Technologies, (1 April 1991); doi: 10.1117/12.25527
Show Author Affiliations
Sol Krongelb, IBM/Thomas J. Watson Research Ctr. (United States)
John O. Dukovic, IBM/Thomas J. Watson Research Ctr. (United States)
M. L. Komsa, IBM/Thomas J. Watson Research Ctr. (United States)
S. Mehdizadeh, IBM/Thomas J. Watson Research Ctr. (United States)
Lubomyr T. Romankiw, IBM/Thomas J. Watson Research Ctr. (United States)
Panayotis C. Andricacos, IBM/Thomas J. Watson Research Ctr. (United States)
A. T. Pfeiffer, IBM/Thomas J. Watson Research Ctr. (United States)
Kason Wong, IBM/Thomas J. Watson Research Ctr. (United States)


Published in SPIE Proceedings Vol. 1389:
Microelectronic Interconnects and Packages: Optical and Electrical Technologies
Gnanalingam Arjavalingam; James Pazaris, Editor(s)

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