Share Email Print
cover

Proceedings Paper

Interconnection problems in VLSI random access memory chip
Author(s): Venkatapathi Naidu Rayapati; Dinkar Mukhedkar
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

This paper presents interconnection problems in VLSI Random Access Memory (RAM) chip. Interconnection effect on propagation delay speed power consumption and noise parameters are analyzed. Interconnect capacitance model is developed for VLSI RAM chip. A case study is presented for 1MB RAM chip interconnection problems. A multilevel interconnect approach is proposed to overcome onchip interconnect problems. The analysis results are found to be very useful for future mega bit RAMs. 98 / SPIE Vol. 1389 International Conference on Advances in Interconnection and Packaging (1990)

Paper Details

Date Published: 1 April 1991
PDF: 12 pages
Proc. SPIE 1389, Microelectronic Interconnects and Packages: Optical and Electrical Technologies, (1 April 1991); doi: 10.1117/12.25513
Show Author Affiliations
Venkatapathi Naidu Rayapati, Ecole Polytechnique (Canada)
Dinkar Mukhedkar, Ecole Polytechnique (Canada)


Published in SPIE Proceedings Vol. 1389:
Microelectronic Interconnects and Packages: Optical and Electrical Technologies
Gnanalingam Arjavalingam; James Pazaris, Editor(s)

© SPIE. Terms of Use
Back to Top