Share Email Print
cover

Proceedings Paper

Effects of packaging and interconnect technology on testability of printed wiring boards
Author(s): Joseph L.A. Hughes; Prem Pahlajrai
Format Member Price Non-Member Price
PDF $14.40 $18.00

Paper Abstract

Continuing improvements in packaging and interconnect technology have made it increasingly difficult to adequately test printed wiring board (PWB) assemblies. Traditional PWB test methods depend on both the relatively small number of components on the board and easy access to the interconnection signal paths. This paper surveys options for verifying correct logical behavior (i. e. ''functional" or " digital'' testing) of state-of-the-art PWBs. Design for Testability (DFT) methods for enhancing circuit observability and controllability are described along with extensions of these methods for board-level testing (such as Built-In Self-Test and the IEEE/JTAG Boundary Scan standard). Testability problems are likely to increase as new packaging and interconnect technologies using ceramics and polyimides further increase circuit density and complexity. This paper considers the impact of these technology advances on current testing strategies and potential alternative methodologies.

Paper Details

Date Published: 1 April 1991
PDF: 11 pages
Proc. SPIE 1389, Microelectronic Interconnects and Packages: Optical and Electrical Technologies, (1 April 1991); doi: 10.1117/12.25512
Show Author Affiliations
Joseph L.A. Hughes, Georgia Institute of Technology (United States)
Prem Pahlajrai, Georgia Institute of Technology (United States)


Published in SPIE Proceedings Vol. 1389:
Microelectronic Interconnects and Packages: Optical and Electrical Technologies
Gnanalingam Arjavalingam; James Pazaris, Editor(s)

© SPIE. Terms of Use
Back to Top