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Status of overlay performance for NIL high volume manufacturing
Author(s): Tatsuya Hayashi; Yukio Takabayashi; Mitsuru Hiura; Takehiko Iwanaga; Hiroshi Morohoshi; Takamitsu Komaki
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Paper Abstract

Nanoimprint lithography (NIL) techniques are known to possess replication resolution below 5nm. A specific form of imprint lithography using jetted resist has been developed for manufacturing advanced CMOS memory. Canon’s NIL process involves field-by-field inkjet deposition of a low viscosity resist fluid followed by imprinting with nano-scale precision overlay. A mask with a relief structure is lowered into the fluid which then quickly flows into the relief patterns in the mask by capillary action. Following this filling step, the resist is crosslinked under UV radiation, and then the mask is separated from the substrate leaving a patterned resist on the substrate. The technology faithfully reproduces patterns with a higher resolution and greater uniformity compared to those produced by photolithography equipment. Additionally, as this technology does not require an array of wide-diameter lenses and the expensive light sources necessary for advanced photolithography equipment, NIL equipment achieves a simpler, more compact design, allowing for multiple units to be clustered together for increased productivity. Previous studies have demonstrated NIL resolution better than 10nm, making the technology suitable for the printing of several generations of critical memory levels with a single mask. In addition, resist is applied only where necessary, thereby eliminating material waste. Given that there are no complicated optics in the imprint system, the reduction in the cost of the tool, when combined with simple single level processing and zero waste leads to a cost model that is very compelling for semiconductor memory applications. Any new lithographic technology to be introduced into manufacturing must deliver either a performance advantage or a cost advantage. Key technical attributes include alignment, overlay and throughput. In previous papers, overlay and throughput results have been reported on test wafers. In this work, improvements to the alignment system, together with the High Order Distortion Correction (HODC) system have enabled better distortion and overlay results on both test wafers and device wafers. The linear response of the HODC system was demonstrated for multiple high order terms and on test wafers, XMMO of 2.9nm and 3.2nm in x and y respectively was achieved. Additionally an SMO of 2.2nm and 2.4nm was achieved, with an opportunity to further improve results by applying wafer chucks with better flatness specifications.

Paper Details

Date Published: 27 June 2019
PDF: 7 pages
Proc. SPIE 11178, Photomask Japan 2019: XXVI Symposium on Photomask and Next-Generation Lithography Mask Technology, 111780J (27 June 2019); doi: 10.1117/12.2536315
Show Author Affiliations
Tatsuya Hayashi, Canon Inc. (Japan)
Yukio Takabayashi, Canon Inc. (Japan)
Mitsuru Hiura, Canon Inc. (Japan)
Takehiko Iwanaga, Canon Inc. (Japan)
Hiroshi Morohoshi, Canon Inc. (Japan)
Takamitsu Komaki, Canon Inc. (Japan)


Published in SPIE Proceedings Vol. 11178:
Photomask Japan 2019: XXVI Symposium on Photomask and Next-Generation Lithography Mask Technology
Akihiko Ando, Editor(s)

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