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Wafer-level inspection platform on high-volume photonic integrated circuits for drastic reduction of testing time
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Paper Abstract

We describe a wafer prober integrated with an optical probe for wafer-level inspection of photonic integrated circuits. The design of the electric and photonic circuit was optimized for wafer-level inspection. The customized prober and circuit design enabled us to perform high-volume and high-speed inspection of over 400 elements, and sufficiently reliable results were obtained. It took about 10 sec. to evaluate the propagation loss of an element. This technology will be a key to reducing the costs of photonic devices.

Paper Details

Date Published: 21 June 2019
PDF: 7 pages
Proc. SPIE 11056, Optical Measurement Systems for Industrial Inspection XI, 110562R (21 June 2019); doi: 10.1117/12.2527382
Show Author Affiliations
Toru Miura, NTT Corp. (Japan)
Yoshiho Maeda, NTT Corp. (Japan)
Shinji Matsuo, NTT Corp. (Japan)
Hiroshi Fukuda, NTT Corp. (Japan)


Published in SPIE Proceedings Vol. 11056:
Optical Measurement Systems for Industrial Inspection XI
Peter Lehmann; Wolfgang Osten; Armando Albertazzi Gonçalves Jr., Editor(s)

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